1. Field of the Invention
The present invention relates generally to a metal programmable integrated circuit and a related method for forming the metal programmable integrated circuit. More specifically, the present invention discloses a metal programmable integrated circuit capable of utilizing a plurality of clock sources and capable of eliminating clock skew and a related method for forming the metal programmable integrated circuit.
2. Description of the Prior Art
In the past, electronic components such as capacitors and resistors are electrically connected with the help of a rigid circuit board. However, semiconductor technology advances integrated circuits. That is, well-known electronic components are fabricated on one chip and the required traces connecting the well-known electronic components are implemented according to the same semiconductor technology.
Recently, the semiconductor technology process has developed to utilize a sub-micro process or a deep sub-micro process for reducing the width of each trace. Therefore, the total number of electronic components on the same chip increases when implementing a more complicated circuit. In the past, a system required many chips with appropriate connections to be capable of fulfilling a predetermined logic operation. However, with advances in the semiconductor process, different circuits can be fabricated on one chip. Therefore, different chips making up the system are integrated so that the total number of chips and total number of external wires are reduced.
For example, the well-known system on a chip (SOC) technology was developed to achieve an objective of using a single chip for implementing a system. However, an IC designer needs more efficient design methodology and powerful computer-aided design tools to accomplish such a complicated chip design successfully and correctly.
The development of integrated circuits accordingly boosts development of electronic products. For instance, the electronic components originally positioned on the circuit board are fabricated within the integrated circuit instead. Compared with a circuit board utilizing metal conductive wires (copper wires for example) to electrically connect two electronic components, the integrated circuit generally utilizes much shorter and much narrower traces to cut down internal parasite capacitance induced from the traces. Therefore, the circuit implemented by an integrated circuit works more accurately than that implemented by a rigid circuit board.
In addition, because many electronic circuits are capable of being integrated into the same integrated circuit, electronic products tend towards a smaller size and lighter weight. Besides, power dissipation and production cost are greatly reduced. Portable devices such as laptop computers and personal digital assistants are popular among consumers, further promoting the development of related portable devices.
Theoretically, the integrated circuit is capable of implementing any circuit on single chip with a small size. However, the size of each kind of integrated circuits differs. A digital integrated circuit has the lowest power dissipation so that the density of the electronic components is greatly improved. Other types of integrated circuits such as analog integrated circuits and radio frequency integrated circuits have higher power dissipation or have wires with turning points that will dissipate power while transmitting high-frequency signals. Therefore, concerning heat radiation or signal transmission, the density of the electronic components is limited for certain kinds of integrated circuit.
In addition, with improvements in circuit design, analog circuits with low power dissipation and high processing speed are capable of being integrated with digital circuits to form mixed-mode integrated circuits. From the above description, the integrated circuits are widely used in all kinds of electronic products, and how to design traces between electronic components inside the integrated circuit has become an important issue.
Because the scale of an integrated circuit expands with the development of semiconductor process, it is difficult for an engineer to handle overall chip manufacturing for a very-large-scale integrated circuit (VLSI). A manufacturing process of the integrated circuit is divided into a semiconductor process, a photomask design, a component test, etc. A well-known pattern independent principle discloses that photomask design and the actual semiconductor process are separated. Geometric allocation of components and traces is designed according to limitations (an allowable spacing width for example) in the applied semiconductor process. That is, the pattern design for the photomask is processed according to well-known design rules. Therefore, the integrated circuit designer does not need to understand the detailed procedures of the semiconductor process when designing any chip composed of integrated circuits.
Similarly, the semiconductor foundry also does not need to understand the detailed functions of the integrated circuit when manufacturing the integrated circuit. With the use of the design rules, the integrated circuit design is isolated from the semiconductor process to simplify the overall manufacturing process of the integrated circuit. In other words, the workload for the integrated circuit designer and that for the chip manufacturer is reduced. If both the integrated circuit designer and the chip manufacturer comply with the same design rules, the manufacture of the chip composed of integrated circuits will correspond to an acceptable yield.
The electronic products nowadays generally adopt application specific integrated circuits (ASICs) to support more functions and to lower production cost. For example, the computer peripheral devices such as hard-disk drives and scanners have application specific integrated circuits installed on the corresponding circuit boards. One objective of the application specific integrated circuit is to integrate required circuits more efficiently, and another objective is to protect aninnovative circuit design from being easily copied by competitors. However, prototype development is a bottleneck when manufacturing the specific integrated circuit.
Recently, people are eagerly searching for a method of quickly developing a prototype used for verifying functions of the designed application specific integrated circuit and debugging the application specific integrated circuit. Therefore, the time-to-market related to the application specific integrated circuit is shortened to improve corresponding competitiveness. The design methodology for the integrated circuits includes a full-custom design, a gate array design, and a standard cell design.
The full-custom design means that the circuit layout design starts from designing fundamental transistors. The integrated circuit designer has to design sizes of components, locations of components, and connections between components in person. This kind of design methodology is capable of acquiring the best performance from the integrated circuit (higher processing speed and lower power dissipation) and greatest component density (smaller chip size). In addition, production cost is accordingly low owing to the smaller chip size. However, the full-custom design requires the most efforts of the integrated circuit designer, and takes a longer period of lead-time.
The standard cell design and the gate array design are respectively used to moderately simplify the design complexity. The standard cell design uses commonly used function blocks pre-defined by a cell library to build a large-scale circuit. Therefore, the main job of the integrated circuit designer is design placement of the function blocks and routing between the function blocks. The cell library is composed of previously developed small-scale circuits. Because functions related to small-scale circuits defined in the cell library have been verified during a previous development process of the small-scale circuits, the combinational large-scale circuit has a great possibility of a correct function and a great yield. In addition, with less efforts spent on the overall circuit design, the lead-time is accordingly shortened.
The principle drawback is that each function block corresponds to a specific structure. Therefore, when many function blocks are formed on the same wafer, each function block requires a unique photomask pattern design. That is, more photomask layers are used to manufacture the function block. In addition, the photomask pattern design for one function block may not be compatible with another function block so that the production cost of the chip is greater. Besides, it is difficult to greatly reduce overall chip size because each function block corresponds to a specific geometric shape.
With regard to the gate array design, a semiconductor foundry provides fixed-size standard transistors and an allowable spacing width between traces. The semiconductor foundry only manufactures standard transistors, that is, a semi-finished production of the chip, which is only composed of a transistor array without metal traces. Therefore, the integrated circuit designer can design traces routing among the standard transistors according to hardware specifications related to the standard transistors. In other words, the principle job of the integrated circuit designer is to program the photomask patterns related to upper metal layers of the integrated circuit. Then, the designed photomask patterns are transferred to the semiconductor foundry for further forming the metal layers to accomplish routing traces among the transistors. In the end, the chip composed of the integrated circuit is generated from the semiconductor foundry. As mentioned above, because each transistor corresponds to the same hardware specification, the photomask pattern is capable of being re-used for forming the transistors so that the photomask cost is greatly lowered.
Please refer to FIG. 1, which is a diagram showing a prior art semiconductor body 10 of an integrated circuit. The semiconductor body 10 has a plurality of functional circuit cells 12. The functional circuit cells 12 are arranged row-by-row or column-by-column according to an array format to finally form a matrix format. It is well-known that the matrix format corresponds to a minimum chip size. That is, the allocation of the functional circuit cells 12 corresponds to a maximum component density.
The semiconductor body 10 is divided into synchronous regions 14a, 14b and a non-synchronous region 16. All of the functional circuit cells 18a, 18b within the synchronous regions 14a, 14b operate according to a clock signal. For example, each of the functional circuit cells 18a, 18b respectively functions as a flip-flop, a latch, or a clock buffer after being defined by a corresponding routing design. On the other hand, the functional circuit cells 20 within the non-synchronous region 16 are not driven by clock signals.
Each functional circuit cell 20 is capable of performing a predetermined logic operation after being defined by a corresponding routing design. For example, each of the functional circuit cells 20 respectively functions as an AND logic gate circuit, an OR logic gate circuit, or an XOR logic gate circuit. According to the gate array design, It is noteworthy that maker of the semiconductor body 10 (the semiconductor foundry for example) does not form any traces routing among the functional circuit cells 12 in the beginning. In other words, connections between contacts of the functional circuit cells 12 are defined according to the photomask patterns programmed by the integrated circuit designer.
After the integrated circuit designer hands over the designed photomask patterns to maker of the semiconductor body 10, upper metal layers are then formed on the semiconductor body 10 based on the photomask patterns. For instance, a first metal layer and a second metal layer are formed on the semiconductor body 10 to place traces routed among the functional circuit cells 12 so that the integrated circuit is capable of correctly performing a predetermined operation. In addition, global traces such as clock traces and power traces are implemented by a third metal layer.
Please refer to FIG. 1 in conjunction with FIG. 2. FIG. 2 is a diagram showing traces routed within the synchronous regions 14a, 14b. In the synchronous region 14a, a clock trace 22a vertically crosses each functional circuit cell 18a of the synchronous region 14a. In addition, two power traces 24a, 26a also cross each functional circuit cell 18a of the synchronous region 14a. The power traces 24a, 26a are respectively used to provide operating voltages (a high voltage level Vdd and a low voltage level Vss for example) required by each functional circuit cell 18a. Similarly, a clock trace 22b and two power traces 24b, 26b vertically cross each functional circuit cell 18b of the synchronous region 14b. As shown in FIG. 2, power traces 24a, 24b, 26a, 26b are respectively located at both sides of the clock traces 22a, 22b so that noise transmitted by the clock traces 22a, 22b interfering with the clock signals is reduced. In other words, clock skew related to the clock signal is lessened.
Because the functional circuit cells 18a, 18b requiring clock signals to function properly are confined to the synchronous regions 14a, 14b, the clock traces 22a, 22b are only positioned within the synchronous regions 14a, 14b. That is, a clock tree corresponding to the semiconductor body 10 is simplified. With proper allocation of the synchronous regions 14a, 14b and the non-synchronous region 16 within the semiconductor body 10 of the prior art integrated circuit, power dissipation and clock skew related to the clock signals transmitted by the clock traces 22a, 22b is then reduced.
Generally speaking, delay time of a signal transmitted by any transmission path within the prior art integrated circuit includes two factors. One factor is a gate delay generated from logic gates, and another factor is a wire delay generated from the length of traces. The two factors respectively correspond to different contributions to the delay time according to the adopted semiconductor process.
With regard to the micro process, the wire delay is negligible. However, with regard to the sub-micro process, size of the electronic component is greatly reduced to lower corresponding gate delay. On the other hand, the wire delay is increased because the width of the trace is narrowed to accordingly increase resistance of the trace. Comparing the wire delay and the gate delay, the wire delay generated from the rising resistance of the trace cannot be neglected anymore. Therefore, the clock skew of the clock traces 22a, 22b needs to be carefully considered.
As mentioned above, the semiconductor body 10 of the prior art integrated circuit is divided into synchronous regions 14a, 14b and a non-synchronous region 16. The functional circuit cells 18a, 18b, driven by the clock signals, are distributed in the synchronous regions 14a, 14b. That is, the prior art has to consider clock balance for controlling clock skew according to the geometric distribution of the synchronous regions 14a, 14b within the semiconductor body 10. However, based on the prior art semiconductor body 10, the geometric distribution of the synchronous regions 14a, 14b corresponds to a predetermined allocation of clock traces 22a, 22b. As shown in FIG. 2, the clock traces 22a, 22b vertically cross all of the functional circuit cells 18a, 18b located at the synchronous regions 14a, 14b. Therefore, the integrated circuit designer has to adopt a fixed amount of clock sources according to the geometric distribution of the synchronous regions 14a, 14b. In other words, the prior art semiconductor body 10 does not allow the integrated circuit designer to adopt any wanted amount of clock sources for the sake of clock balance. To sum up, the application field of the semiconductor body 10 is limited by the geometric distribution of the synchronous regions 14a, 14b. 